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Synopsys, Inc. (Nasdaq:SNPS) has announced a groundbreaking advancement with the introduction of the industry’s first complete 40G UCIe IP solution, designed to meet the growing demands of high-performance AI data centers. This innovative solution operates at speeds of up to 40 Gbps per pin, addressing the need for enhanced compute performance and efficient die-to-die connectivity in multi-die systems.
The UCIe (Universal Chiplet Interconnect Express) standard has become essential for high-bandwidth, low-latency communication between dies, or chiplets, within a single package. The new Synopsys 40G UCIe IP solution is a comprehensive package that includes PHY, controller, and verification IP components. It supports both organic substrate and advanced high-density packaging technologies, offering designers flexibility in their choice of packaging options.
This complete 40G UCIe IP solution is a critical element in Synopsys’ extensive multi-die solution portfolio, which facilitates fast heterogeneous integration from initial architecture exploration through to final manufacturing. By providing the highest bandwidth for die-to-die connections, Synopsys aims to significantly enhance the performance of AI data center chips.
Jongwoo Lee, Vice President of the System LSI IP Development Team at Samsung Electronics, emphasized the importance of this technology, stating, "Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications. Leveraging Synopsys' new 40G UCIe IP, we can extend our collaboration to develop industry-leading chiplet solutions for tomorrow's high-performance data centers."
Michael Posner, Vice President of IP Product Management at Synopsys, highlighted the company's commitment to semiconductor innovation, saying, "Launching the industry's first complete 40G UCIe IP solution underscores Synopsys' continued investment in advancing semiconductor technology. Our active contribution to the UCIe consortium has enabled us to deliver a robust solution that supports our customers in developing and optimizing their multi-die designs for high-performance AI computing systems."
Key features of the new Synopsys 40G UCIe IP solution include:
- Simplified Integration: The single reference clock architecture streamlines clocking and optimizes power, facilitating quicker die-to-die link initialization without firmware loading.
- Silicon Health Monitoring: Integrated test and silicon lifecycle management features ensure reliability across die, die-to-die, and multi-die package levels, with tools for monitoring, testing, and analysis.
- Ecosystem Interoperability: Supports popular on-chip interconnect fabrics such as AXI, CHI, PCI Express, and CXL, and is compliant with UCIe 1.1 and 2.0 standards.
- Pre-Verified Design Flow: Paired with Synopsys' 3DIC Compiler, this IP is part of a pre-verified design reference flow that includes automated routing, interposer studies, and signal integrity analysis.
- Broad IP Solutions: Synopsys also offers HBM3 and 3DIO IP, complementing the UCIe IP to enable high-capacity memory and advanced 3D packaging solutions.
With these advancements, Synopsys continues to lead in semiconductor innovation, providing critical tools for the development of next-generation AI data centers.
